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in the trail the files are as listed below. 3GMOB board plus.U.S. Pat. No. 4,018,854, issued Apr. 19, 1977 to H. Lemmon et al., discloses and claims a semiconductor wafer that has an annular groove between two faces thereof to provide a passage for ionized gases released by the wafer during an annealing step. The passage is not always centered with respect to the wafer but is instead formed with an annular gas distribution edge extending along a partial circumference of each face of the wafer.
U.S. Pat. No. 4,713,173, issued Dec. 15, 1987 to S. Z. Cardin, discloses and claims a semiconductor wafer having an annular groove along a peripheral edge thereof for release of gaseous contaminants during processing. The groove is formed by making a series of sequential grooves in a passivation film of a wafer.
U.S. Pat. No. 4,743,267, issued May 10, 1988 to E. Castano, discloses and claims a semiconductor wafer having a depression formed along its edge for the release of contaminants during processing.
U.S. Pat. No. 5,059,444, issued Oct. 22, 1991 to W. A. Anderson et al., discloses and claims a semiconductor wafer having an annular groove formed in its edge for release of an annealing gas during an annealing step. The groove is formed along the edge by performing anisotropic etching of the wafer.
U.S. Pat. No. 5,041,539, issued Aug. 20, 1991 to M. A. Ponzoni et al., discloses and claims a method for uniformly flattening a semiconductor wafer in a silicon dioxide interlayer insulating film formed on the wafer. A first planarizing process is performed on a major surface of the wafer to remove substantially all of the silicon dioxide. A second planarizing process is then performed on the major surface of the wafer to remove silicon dioxide from the edge portion of the wafer but leave silicon dioxide in the center of the wafer. A cover sheet is then placed over the major surface of the wafer.
U.S. Pat. No. 5,055,384, issued Oct. 8, 1991 to A. J. DiMaio et al., discloses
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